# packages

pkgId: cf0a5d28985453ca343baa74b28eb2cd55a3a9c7f09f2148b327d8f1114a2989
name: coriolis-eda
arch: src
version: 2.5.5
epoch: 0
release: 193.1.f4c1b74de
summary: Coriolis 2 EDA toolchain
url: https://coriolis.lip6.fr/
rpm_license: BSD-1-Clause AND LGPL-2.0-only AND GPL-2.0-only AND Apache-1.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: reproducible
rpm_packager: Mazher Iqbal <mazher@lip6.fr>
location_href: src/coriolis-eda-2.5.5-193.1.f4c1b74de.src.rpm
checksum_type: sha256
description:
  A FOSS EDA tool suite for physical design. Provides an integrated
  place & route for ASICs. Support symbolic layout (Alliance) and
  real layout (GDS). While mainly written in C++, it has an extensive
  Python interface.


pkgId: b9cdf913d299d4068c360ae6ff9777c0f0f122979ed22661c6eb6c662fc4bbb8
name: coriolis-pdk-gf180mcu
arch: src
version: 2025.07.21
epoch: 0
release: 4.2.bfa7190
summary: Global Foundries 180 MCU open PDK
url: https://github.com/google/gf180mcu-pdk.git
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: reproducible
location_href: src/coriolis-pdk-gf180mcu-2025.07.21-4.2.bfa7190.src.rpm
checksum_type: sha256
description:
  The GF180MCU  open source PDK  is a collaboration between  Google and
  GlobalFoundries to  provide a  fully open  source process  design kit
  (PDK)  and  related  resources  to enable  the  creation  of  designs
  manufacturable at GlobalFoundries's facility  on their 0.18um 3.3V/6V
  MCU process technology.

  The GF180MCU documentation can be found at <https://gf180mcu-pdk.rtfd.io>.


pkgId: 7c165a17910cccffae9a1a497f113857386f18aec6fd2359b479460cf157b422
name: coriolis-pdk-ihpsg13g2
arch: src
version: 2024.10.15
epoch: 0
release: 27.11.bfa7190
summary: IHP Open PDK SG13G2
url: https://github.com/IHP-GmbH/IHP-Open-PDK
rpm_license: Apache-2.0
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: reproducible
location_href: src/coriolis-pdk-ihpsg13g2-2024.10.15-27.11.bfa7190.src.rpm
checksum_type: sha256
description:
  130nm  BiCMOS Open  Source PDK,  dedicated for  Analog/Digital, Mixed
  Signal and RF Design

  IHP Open  Source PDK project  goal is to  provide a fully  open source
  Process  Design Kit  and related  data, which  can be  used to  create
  manufacturable  designs at  IHP’s facility.   As of  March 2023,  this
  repository is targeting the SG13G2 process node


pkgId: fae65eb2d7db18268d56fd898799d215318b3fe1823617be959b94ebfab63694
name: ngspice
arch: src
version: 44.2
epoch: 0
release: 1.10
summary: Mixed-level, Mixed-signal Circuit Simulator Based on spice3f5
url: https://ngspice.sourceforge.io
rpm_license: BSD-2-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Productivity/Scientific/Electronics
rpm_buildhost: reproducible
location_href: src/ngspice-44.2-1.10.src.rpm
checksum_type: sha256
description:
  Ngspice is a mixed-level/mixed-signal circuit simulator. Its code
  is based on three open source software packages: Spice3f5, Cider1b1
  and Xspice.


pkgId: b34a4522a09e55c0406d195752774680f97309617b0075a9e3d3636ee1637c32
name: openvaf
arch: src
version: 23.5.0
epoch: 0
release: 5.1
summary: OpenVAF is a Next-Generation Verilog-A compiler
url: https://openvaf.semimod.de/
rpm_license: GPL-3.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: reproducible
location_href: src/openvaf-23.5.0-5.1.src.rpm
checksum_type: sha256
description:
  Circuit simulators play a critical role in the design of electrical circuits.
  Accurate simulations enable circuit designers to validate circuit behavior
  before actual fabrication happens, potentially saving significant re-design
  costs.  The simulation of a circuit critically depends on the so-called compact
  models and therefore:
  * The accuracy of the compact-model equations
  * The quality of the model parameters


pkgId: 5c386e5a2a15b2db359440851ef369373ef40c838faef04b6fae2449da9da6a7
name: sv2v
arch: src
version: 0.0.12
epoch: 0
release: 1.1
summary: sv2v - SystemVerilog to Verilog
url: https://github.com/zachjs/sv2v/
rpm_license: BSD-3-Clause
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: reproducible
location_href: src/sv2v-0.0.12-1.1.src.rpm
checksum_type: sha256
description:
  sv2v converts SystemVerilog (IEEE 1800-2017) to Verilog (IEEE 1364-2005),
  with an emphasis on supporting synthesizable language constructs.
    The primary goal of this project is to create a completely free and
  open-source tool for converting SystemVerilog to Verilog. While methods
  for performing this conversion already exist, they generally either rely
  on commercial tools, or are limited in scope.
    This project was originally developed to target Yosys, and so allows for
  disabling the conversion of (passing through) those SystemVerilog features
  that Yosys supports.


pkgId: 05fc58cf07e652886347f2f37246d30af6f8c7752fcf82099320362183182c3f
name: tas-yagle
arch: src
version: 3.4.6
epoch: 0
release: 10.1.ea2ced1
summary: Tas/Yagle - Static Timing Analyser
url: https://coriolis.lip6.fr/
rpm_license: GPL-2.0-only
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: reproducible
location_href: src/tas-yagle-3.4.6-10.1.ea2ced1.src.rpm
checksum_type: sha256
description:
  STATIC TIMING ANALYSIS
    The  advent   of  semiconductor  fabrication  technologies   now  allows  high
  performance in complex integrated circuits.
    With the increasing complexity of these circuits, static timing analysis (STA)
  has  revealed  itself  as  the  only  feasible  method  ensuring  that  expected
  performances are actually obtained.
    In addition, signal integrity (SI) issues due to crosstalk play a crucial role
  in performance and reliability of these  systems, and must be taken into account
  during the timing analysis.
    However, performance  achievement not  only lies in  fabrication technologies,
  but also  in the way circuits  are designed.  Very high  performance designs are
  obtained with semi or full-custom designs techniques.
    The HITAS platform provides advanced STA and SI solutions at transistor level.
  It has been  built-up in order to allow engineers to  ensure complete timing and
  SI coverage on their digital custom  designs, as well as IP-reuse through timing
  abstraction.
    Furthermore,  hierarchy  handling  through  transparent  timing  views  allows
  full-chip verification, with virtually no limit of capacity in design size.


pkgId: 445d4779411bc810aaa74c4fe9d3dcdb06ce6edd7343f8cec5f11be62344545b
name: yosys
arch: src
version: 0.46
epoch: 0
release: 21.12.e97731b9d
summary: Yosys open synthesis suite
url: https://yosyshq.net/yosys/
rpm_license: ISC
rpm_vendor: obs://build.opensuse.org/home:jpc-lip6
rpm_group: Applications/Engineering
rpm_buildhost: reproducible
location_href: src/yosys-0.46-21.12.e97731b9d.src.rpm
checksum_type: sha256
description:
  This is a framework for RTL synthesis tools. It currently has
  extensive Verilog-2005 support and provides a basic set of
  synthesis algorithms for various application domains.

  Yosys can be adapted to perform any synthesis job by combining
  the existing passes (algorithms) using synthesis scripts and
  adding additional passes as needed by extending the yosys C++
  code base.

  Yosys is free software licensed under the ISC license (a GPL
  compatible license that is similar in terms to the MIT license
  or the 2-clause BSD license).


