# /*------------------------------------------------------------\
# |                                                             |
# | File   :                     README                         |
# |                                                             |
# | Author :                 Jacomme Ludovic                    |
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# \------------------------------------------------------------*/

This directory contains the VHDL description of an adder 4 bits and
the associated stimuli file, and also a configuration file for IO
placement (used during the Place and Route step).

The Makefile set environement variables properly and run Alliance tools, 
following each step of the design flow from VHDL up to real layout in a
 pseudo 0.35 techno.

The environement variable ALLIANCE_TOP has to be set.

The main targets of the makefile are listed below (following the design flow).

#
# RTL SYNTHESIS
#

adder4.vbe      : Run the VHDL analyzer (VASY) on the VHDL description 
                  (adder4.vhdl) and transform it into a boolean network (adder4.vbe).

res_vasy_1.pat  : Run the VHDL simulator (ASIMUT) on adder4.vbe using the pattern/stimuli file 
                  adder4.pat. This step checks if the adder4.vbe description is working properly.

xpat_vasy       : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat 

adder4_o.vbe    : Run the Boolean network optimizer (BOOM) on the adder4.vbe and 
                  factorize/minimize boolean equations, and generate a new description
                  adder4_o.vbe.

adder4_o.vst    : Run the boolean mapper (BOOG) on the optimized description adder4_o.vbe
                  and using the sxlib standard cell library, map all boolean nodes to
                  an equivalent set of standard cells.

xsch_adder4_o   : Run the schematic viewer (XSCH) on the structural netlist adder4_o.vst


adder4.vst      : Run the net optimizer (LOON) on the structural description adder4_o.vst.
                  It inserts buffers on the critical path using the sxlib standard cell library
                  and generates a new structural netlist adder4.vst .

xsch_adder4     : Run the schematic viewer (XSCH) on the bufferized netlist adder4.vst .
                  The critical path would be displayed in red color.

res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description adder4.vst using 
                  the pattern/stimuli file adder4.pat and the behavioral description (.VBE) of each 
                  cells of the standard cell library (sxlib).
                  This step checks if the adder4.vst description is still working properly.

#
# PLACE AND ROUTE
#

adder4_p.ap     : Run the placement tool (OCP) on the structural description adder4.vst. 
                  It generates a physical placement file (adder4_p.ap) that would be given
                  to the router (NERO).

graal_adder4_p  : Launch the physical layout editor (GRAAL) and display the result of the placement tool
                  (adder4_p.ap).

adder4.ap       : Run the router tool (NERO). Given the structural description adder4.vst, the
                  placement file (adder4_p) and the position of external connectors (adder4.ioc) 
                  the router generates a physical view (adder4.ap) where all nets have been routed.

graal_adder4    : Launch the physical layout editor (GRAAL) and display the result of the router tool
                  (adder4.ap).

#
# Netlist / parasitics extraction
#

adder4_e.al     : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic
                  informations (physical parameters are taken in the techno-035.rds file).
                  This tool generates the extracted netlist adder4_e.al

xsch_adder4_e   : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (adder4_e.al).

adder4_et.al    : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level 
                  with parasitics informations (adder4_et.al).

xsch_adder4_et  : Run the schematic viewer (XSCH) on the extracted transistor netlist (adder4_et.al).

#
# Netlists comparison
#

lvx.done        : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as
                  the structural structural netlist. This step checks if the place and route phases are ok.

#
# Design rule checker
#

druc.done       : Launch the design rule checker on the layout generated by the router (adder4.ap). The design
                  rules are specified in the RDS file (techno-symb.rds).
                  

#
# Symbolic layout to real layout
#

adder4.cif      : Transforms the symbolic layout in lambda (adder4.ap) in a 0.35u real layout using the tool S2R.
                  It generates a CIF file (adder4.cif).

dreal_adder4    : Launch the real layout editor (DREAL) and display the result of S2R
                  (adder4.cif).


#
# Clean

The clean target remove all generated files ...
