
--
-- Generated by VASY
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;

ENTITY oa2ao222_x4 IS
PORT(
  i0	: IN STD_LOGIC;
  i1	: IN STD_LOGIC;
  i2	: IN STD_LOGIC;
  i3	: IN STD_LOGIC;
  i4	: IN STD_LOGIC;
  q	: OUT STD_LOGIC
);
END oa2ao222_x4;

ARCHITECTURE RTL OF oa2ao222_x4 IS
BEGIN
  q <= ((i0 AND i1) OR (i4 AND (i2 OR i3)));
END RTL;
